A typical circuit board includes multiple semiconductor and other electronic devices. For most of the signals traveling between these devices, timing considerations are increasingly important as the speeds of the devices are increased. For example, with a 16-bit data bus between two or more devices, the signal on each line of the bus should arrive at a receiving device at approximately the same time to avoid timing problems with the device. At higher speeds, this becomes more difficult to control.
Semiconductor devices typically include internal timing delay mismatches due to package constraints. For example, referring now in detail to the drawings, wherein like parts are designated by like reference numerals throughout, FIG. 1 is a plan view illustrating a simplified prior art semiconductor device 50. Semiconductor device 50 includes a semiconductor die 40 embedded in a package 10. Package 10 includes a plurality of pins or balls 12-15 that couple semiconductor device 50 to a circuit board. The signals output from pins 12-15 form a single group (e.g., a data bus).
Pins 12-15 are coupled to die 40 via lead fingers 20-23, respectively. In a typical package such as package 10, the lengths of lead fingers 20-23 vary among different pins due to, for example, the position of pins 12-15 and the route each lead finger 20-23 must take from die 40 to pins 12-15 (e.g., a lead finger may have to weave around other pins or traverse several layers in package 10). The disparity in length between lead fingers can sometimes be over one inch.
Die 40 includes a plurality of output drivers 30-33 corresponding to each pin 12-15. Die 40 further includes a plurality of die pads 34-37 for each output driver 30-33. Output drivers 30-33 are coupled to die pads 34-37 via a metal trace (e.g., metal trace 42), which is referred to as a "standard metal trace" for the purpose of this patent. The length of the standard metal traces are typically the shortest distance between their corresponding die pad and output driver. Die pads 34-37 are coupled to lead fingers 20-23 via a bond wire (e.g., bond wire 44) or directly coupled using known methods.
In most advanced semiconductor devices, die 40 is designed or tuned so that the group of output signals measured at pads 34-37 are matched to within 10 picoseconds ("ps") of each other (i.e., all of the signals arrive at pads 34-37 within a 10 ps window). Adjustments to die 40 to achieve this matching level typically occur within die 40 below output drivers 30-33.
However, when die 40 is placed in package 10, the signals must travel through lead fingers 20-23 before exiting device 50 onto a circuit board. The differing lengths of lead fingers 20-23 add differing propagation delays to the signals when the signals arrive at pins 12-15. For example, if lead finger 20 is one inch longer than lead finger 22, an additional 200 ps of timing delay may be added to the signal traveling on lead finger 20 compared to the signal traveling on lead finger 22. Therefore, because of the disparity between the lengths of lead fingers 20-23, the group of signals are no longer matched within 10 ps when they arrive at pins 12-15. This timing mismatch must then be compensated for in the circuit board, which adds to the complexity of designing the circuit board.
Based on the foregoing, there is a need for a semiconductor device in which the timing of a group of the output signals is matched at the pins.